Lead end‑to‑end system performance strategy and sign‑off for server‑class SoCs across pre‑silicon and early‑silicon platforms. Own performance methodology, benchmarking, and deep‑dive analysis of CPU, memory, NoC, IO, and power‑performance trade‑offs. Provide architecture‑level insights, drive design decisions, translate features into quantitative projections, and mentor engineers. Requires 10+ years in SoC/system performance with strong micro‑architecture and memory/interconnect expertise. Preferred experience: server/data‑center SoCs, cache‑coherent fabrics (CHI/ACE), scalable memory hierarchies, PCIe/CXL, and RUMI/emulation‑based pre‑silicon sign‑off. Works independently with major product impact.